1 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. www.intersil.com or 407-727-9207 | copyright ? intersil corporation 1999 satellite applications flow? (saf) is a trademark of intersil corporation. hcs74t radiation hardened dual-d flip-flop with set and reset intersils satellite applications flow tm (saf) devices are fully tested and guaranteed to 100krad total dose. these qml class t devices are processed to a standard ?ow intended to meet the cost and shorter lead-time needs of large volume satellite manufacturers, while maintaining a high level of reliability. the intersil hcs74t is a radiation hardened positive edge triggered flip-flop with set and reset. the hcs74t utilizes advanced cmos/sos technology to achieve high-speed operation. this device is a member of radiation hardened, high-speed, cmos/sos logic family. speci?cations speci?cations for rad hard qml devices are controlled by the defense supply center in columbus (dscc). the smd numbers listed below must be used when ordering. detailed electrical speci?cations for the hcs74t are contained in smd 5962-95782. a hot-link is provided from our website for downloading . www.intersil.com/spacedefense/newsafclasst.asp intersils quality management plan (qm plan), listing all class t screening operations, is also available on our website. www.intersil.com/quality/manuals.asp features ? qml class t, per mil-prf-38535 ? radiation performance - gamma dose ( g ) 1 x 10 5 rad(si) - latch-up free under any conditions, sos process - sep effective let no upsets: >100 mev-cm 2 /mg - single event upset (seu) immunity < 2 x 10 -9 errors/bit-day (typ) ? 3 micron radiation hardened sos cmos ? signi?cant power reduction compared to lsttl ics ? dc operating voltage range: 4.5v to 5.5v ? input logic levels -v il = 30% of v cc max -v ih = 70% of v cc min ? input current levels ii 5 m a at v ol , v oh pinouts hcs74t (sbdip), cdip2-t14 top view hcs74t (flatpack), cdfp3-f14 top view ordering information ordering information part number temp. range ( o c) 5962r9578201tcc hcs74dtr -55 to 125 5962r9578201txc HCS74KTR -55 to 125 note: minimum order quantity for -t is 150 units through distribution, or 450 units direct. r1 d1 cp1 s1n q1 q1n gnd v cc r2n d2 cp2 s2n q2 q2n 1 2 3 4 5 6 7 14 13 12 11 10 9 8 14 13 12 11 10 9 8 2 3 4 5 6 7 1 r1 d1 cp1 s1 q1 q1 gnd v cc r2 d2 cp2 s2 q2 q2 data sheet july 1999 file number 4615.1
2 functional diagram truth table inputs outputs set reset cp d q q lhxxhl hlxxlh llxxh ? h ? hh hhl hh l lh hhl xq0 q0 note: l = logic level low, h = logic level high, x = dont care = transition from low to high level q0 = the level of q before the indicated input conditions were established. ? this con?guration is non-stable, that is, it will not persist when set and reset inputs return to their inactive (high) level. 4(10) p n 2(12) cl cl p n cl cl 3(11) p n cl cl p n cl cl cl cl 6(8) 5(9) q q s d r 1(13) cp hcs74t
3 all intersil semiconductor products are manufactured, assembled and tested under iso9000 quality systems certi?cation. intersil semiconductor products are sold by description only. intersil corporation reserves the right to make changes in circuit design and/or spec ifications at any time with- out notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is b elieved to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of th ird parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see web site http://www.intersil.com die characteristics die dimensions: (2261 m m x 2235 m m x 533 m m 51 m m) 89 x 88 x 21mils 2mil metallization: type: al si thickness: 11k ? 1k ? substrate potential: unbiased (silicon on sapphire) backside finish: sapphire passivation: type: silox (s i o 2 ) thickness: 13k ? 2.6k ? worst case current density: < 2.0e5 a/cm 2 transistor count: 192 process: cmos sos metallization mask layout hcs74t r1 v cc cp1 (3) s1 (4) q1 (5) q1 (6) (8) (9) (10) s2 (11) cp2 (12) d2 (13) r2 (1) (14) q2 q2 d1 (2) nc nc (7) gnd hcs74t
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